1. Field of the Invention
This invention relates to the field of digital circuitry, particularly to area of master-slave flip-flops. More specifically, the present invention relates to the area of data latches.
2. Description of the Related Art
The performance of microprocessors and other synchronous devices has been limited by the power dissipation of these devices. It has been observed that a significant amount of power dissipation is generated by the clock line. Therefore, a reduction in the power dissipation of the clock line may greatly decrease the power dissipation of a device. The power dissipation of the clock line may be calculated by the following equation: EQU power dissipation=capacitance.times.frequency.times.voltage.sup.2
As can be seen from this equation, a decrease in the capacitance on the clock line will decrease the power dissipation of the clock line.
In addition, the frequency at which microprocessors and other synchronous devices are able to operate has been limited by clock skew. Clock skew is the degree to which clock pulses throughout a synchronous device are out of synchronization. The greater the frequency of the clock, the smaller the clock skew must be kept to maintain synchronization of the device. It has been observed that clock skew decreases as capacitance on the clock line is decreased. Thus, reducing capacitance on the clock line may allow microprocessors and other large synchronous circuits to operate at higher clock frequencies.
Capacitance on the clock line is generated in part by master-slave flip-flops. A master-slave flip-flop is composed of two data latches, referred to as the master latch and the slave latch, which are both connected to the clock line. There are many well known circuits for providing master-slave flip-flops. A first prior art method, having a low capacitance on the clock line, is shown in FIG. 8. However, this prior art method suffers from several problems. One such problem is the loss of data due to glitches in the clock signal caused by coupling. For example, while the clock signal asserted on clock line 830 is high and storage portion 870 is storing a high data signal, glitches in the clock signal will temporarily open p-channel transistor 845 and discharge node 875. As a result, the data signal stored in storage portion 870 is lost. Another such problem is the poor passage of data signals asserted on data line 835 due to the use of single transistors for pass gate 840 and pass gate 850. For example, the data signal asserted on data line 835 is passed by pass gate 840, which is composed of single p-channel transistor 845. However, p-channel transistors pass Vcc well, but pass Vss poorly. This limits the speed and the reliability of this flip-flop severely. Finally, contention is experienced when the values stored in storage portion 870 and storage portion 880 differ from the data signals being passed by pass gate 840 and pass gate 850, respectively. Due to these problems, this prior art method is not acceptable for most applications.
A second prior art method that overcomes the aforementioned problems experienced by the first prior art method is shown in FIG. 9. With reference to FIG. 9, master-slave flip-flop 900 comprises master latch 910 and slave latch 920. To suppress glitches experienced by the first prior art method, inverter 960 is added to clock line 930. In addition, to properly pass the data signals asserted on data line 935, pass gate 840 and pass gate 850 are replaced with complimentary pass gate 940 and complimentary pass gate 945, respectively, which pass both Vcc and Vss well. However, because complimentary pass gate 940 and complimentary pass gate 945 contain complimentary devices, inverter 965 is also added to clock line 930 to supply the appropriate clock signal. Finally, to reduce contention which results when the data signal being asserted differs from the signals stored in storage portion 970 and storage portion 980, a tri-state inverter or a pass gate, such as pass gate 975 and pass gate 985, is included.
Although this second prior art method solves the problems with the first prior art method, the large number of transistors and complex routing utilized by this second prior an method result in an excessive amount of capacitance on clock line 930. As a result, the use of this second method in microprocessors and other synchronous circuits results in excessive clock skew and unnecessary power dissipation on the clock line.